Due to the concern of individuality and portability of electronic devices, package technology has been developed to CSP (Chip Scale Package). It is characterized by the reduced size of IC packaging. The size of packaging depends on the size of die, which means the length of packaged IC will not be longer than 1.2 times of the length of die, and the measurement of packaged IC will not be bigger than 1.4 times of the measurement of die.

CDFN (Chip Scale Dual Fine-pitch No-lead) package is an innovative technology developed by SiS. It originally comes from Lead Frame Type, which is one of CSP (Chip Scale Package), and further, integrates with the concept of RoHS compliance to become a creative package technology. CDFN package technology will be presented to public in Q4 2006 through the announcement of SiS DDR2-800 memory.

CDFN features:

1. Fulfill the need of keeping increasing I/O pin count.
2. The scale ratio between IC and packaged IC is pretty small.
3. Shrink the delay in the transmission of data.

CDFN package is suitable for the use in low pin count IC, such as memory modules and the chips of portable devices. It will be greatly applied in emerging products covering IA, DTV, E-Book, WLAN/Gigabit Ethernet, ADSL/Cell phone chip, and Bluetooth in the future.