The
performance of many current applications directly
depends on the latency of data access between the
CPU and I/O devices especially when single stream
is used in the application. These applications include
single Internet Web access, email transmission through
the Internet and all direct single I/O accesses.
Thus, we want to show that our system has the lowest
latency when the single stream access type is used
in HyperStreaming architecture. A new real-time
operation system (RTOS) is created to avoid any
interference between measurements that a WindowsR
O/S may give. On the other hand, we can read from
the CPU embedded-registers to get related performances
based on the well-known concept of clock cycles
per instruction (CPI).
The platform is tested with a AMD AthlonTM XP 2400+
CPU and 256MB DDR333 DRAM. As shown in Fig.2(a),
(b), (c) and (d), our system is more than capable
to deliver latencies low enough for various types
of accesses.
Clock Cycles Per Instruction(CPIs) |
