The SiS740 integrates a high performance and high quality 3D/2D Graphical Accelerator, Video Accelerator and Motion Compensation MPEG1/MPRII Video Decoder for the AMD Socket A series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth demand form the integrated GUI, host processor, as well as the multi I/O masters. A wide bandwidth and high throughput MuTIOL® Connect is incorporated to interconnect the SiS740 to a series SiS961 MuTIOL® Media I/O.

The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture and Geometry Transform/lighting engines, and a 128-bit 2D accelerator with 1T pipeline BITBLT engine. It also features a Video high quality DVD playback. A 12 bit DDR digital video link interfaced to SiS301 package in 100-pin PQFP is incorporated to expand the SiS 740 functionality in support of the secondary display, in addition to the default primary CRT display. The SiS301 Video Bridge integrates an NTSL/PAL video encoder with Macro Vision V7.1.L1 option for TV display, A TMDS transmitter with Bi-linear scaling capability for TFT LCD panel support, and an analog RGB port to support a secondary CRT. The primary CRT display and the extended secondary display (TV, TFT LCD Panel, 2nd CRT) features the Dual View capability in the sense that both can generate the display in independent resolutions, color depths, and frame rates.

The SiS740 Host Interface features the S2K complaint bus driver technology to support AMD Polamino, Athlon, and Duron processors. It also supports the AMD PowerNow™ dynamic power management technique. A Unified Memory Controller supporting SDR-133 or DDR-266 Dram is incorporated, delivering a high performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphical accelerator, or the I/O bus masters. The memory controller also supports the Suspend-to-RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source delivers power. The SiS740 adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.

Two separate buses, Host-t-GUI in the width of 64-bits, and GUI-t-Memory Controller in the width of 128 bit are devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In SDR133, or DDR266 memory subsystem, the 128-bit GUI-t-MC bus will attain the AGP 4X or AGP 8X equivalent texture transfer rate, respectively. The Integrated Memory Controller mainly comprises the Memory Arbiter, the M-data/M-CoMmanD Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI, Host Controller, and I/O bus masters based on a default optimi zed priority list with the capability of dynamically prioritizing the I/O bus master requests in a bit to offering privileged service to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the max. tolerate period of 10us. Prior to the memory access request pushed into the M-data queue, any command complaint to the paging mechanism is generated and pushed into the M-CMD queue. The M-Data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by scheduling command requests in the background when the data requests streamlines in the foreground.