Integrated Fast Ethernet controller and 10/100 megabit per second (Mbps) Physical Layer Transceivers for the PCI local bus
- PCI specification revision 2.1 compliant 
- 32-bit glueless PCI host interface 
- Plug and Play compatible
- Supports PCI clock frequency from DC to 33 MHz independent of network clock
- Supports network operation with PCI clock from 25Mhz to 33Mhz
- Supports both +3.3v and +5v PCI signaling
- High-performance 32-bit PCI bus master architecture with an integrated Direct 
 
Memory Access (DMA ) Controller for low CPU and bus utilization - Supports an unlimited PCI burst length 
- Supports big endian and little endian byte alignments
- Supports PCI Device ID, Vendor ID/Subsystem ID, Subsystem Vendor ID 
 
Programming through the EEPROM interface
- Implements optional PCI 3.3v auxiliary power source 3.3Vaux pin and optional
 
PCI power management event (PME#) pin 
- IEEE 802.3 and 802.3u standard compatible
- IEEE 802.3u Auto Negotiation and Parallel detection for automatic speed 
 
Selection 
- Full duplex and half duplex mode for both 10 and 100 Mbps. 
- Fully compliant ANSI X3.263 TP-PMD physical sub-layer which includes adaptive 
 
Squalization and Baseline Wander compensation.  - Automatic Jam and IEEE 802.3x Auto-Negotiation for flow control
- Flexible hardware and software interrupt capability
- Single access to complete PHY register set
- Built-in waveform shaping requires no external filters 
- Single 25Mhz clock for 10 and 100 Mbps operation.
- Power down of 10Base-T/100Base-TX sections when not in use
- Jabber control and auto-polarity correction for 10Base-T. 
- User programmable LED function mapping
- Supports software, enhanced software, and automatic polling schemes to internal PHY status monitor and interrupt
- Supports 10BASE-T, 100BASE-TX, and any future 
 
Supports PC97, PC98, and Net PC requirements - Green PC compatible 
- Supports Advanced Configuration and Power Interface Specification (ACPI) Revision 1.0
- Supports PCI Bus Power Management Interface Specification Version 1.0a
- Supports Network Device Class Power Management Specification Version 1.0a 
- Supports PCI Hot-Plug Specification Revision 1.0
- Implements full OnNow features including pattern matching and link status wake-up with automatic internal PHY status polling
- Implements optional Magic PacketTM remote wake-up scheme 
- Implements IEEE 802.3x compliant Flow Control 
 
Additional features 
- Internal 128-bit Multicast Hash Table address filter 
- Serial EEPROM support 
- FLASH Boot ROM supports up to 128 Kbytes
- Extensive programmable internal/external loopback capabilities
- +3.3V power supply with +5V tolerant I/Os
- Low-Power CMOS 0.35um Technology 
- 128-pin PQFP package