The SiS965L MuTIOL® 1G Media I/O integrates two PCI Express 1.0a root complex x1 ports, one Universal SerialBus 2.0 Host Controllers, the Audio Controller with AC'97 Interface, the Ethernet MAC Controller w/ standard MIIinterface, three Universal Serial Bus 1.1 Host Controllers, the IDE Master/Slave controllers, 2 ports Serial ATA Host Controller and SiS MuTIOL® 1G technology. The PCI to LPC bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O and legacy power management functionalities are integrated as well.The high-speed host controller implements an EHCI compliant interface that provides 480Mb/s bandwidth for eight USB 2.0 ports. The three USB1.1 host controllers implement an OHCI compliant interface and each USB1.1 host controller provides 12Mb/s bandwidth. The totally eight USB ports can be automatically routed to support a High-speed USB 2.0 device or Full- or Low-speed USB 1.1 device. Besides, each port can be optionally configured as the wake-up source. Legacy USB devices as well as over current detection are also implemented.

The Integrated AC'97 v2.3 compliance Audio Controller that features a 8-channels of audio speaker out and v.90 modem support. Additionally, the AC'97 interface supports 4 separate SDATAIN pins that are capable of supporting multiple audio codecs with one separate modem codec.

The integrated Ethernet MAC Controller features an IEEE 802.3 and IEEE 802.3x compliant MAC with external LAN physical layer chip supporting full duplex 10 Base-T, 100 Base-T Ethernet or with external Home networking physical layer chip supporting 1Mb/s & 10Mb/s Home networking. Additionally, 8 wake-up Frames, Magic Packet and link status changed wake-up function in G1/G2 states are supported. For storing Mac address, two schemes are provided: 1. Store in internal APC register or 2. Store in external EEPROM.

The integrated IDE Master/Slave controllers feature Dual Independent IDE channels supporting PIO mode 0,1,2,3,4, and Ultra DMA 33/66/100/133. It provides two separate data paths for the dual IDE channels that sustain the high data transfer rate in the multitasking environment.

The integrated Serial ATA Host Controller features two SATA ports. It complies with SATA 1.0 specification and supports 1.5Gb/sec bandwidth for each serial port. SiS965L supports 6 PCI masters and complies with PCI 2.3 specification. It also incorporates the legacy system I/O like: two 8237A compatible DMA controllers, three 8254 compatible programmable 16-bit counters, hardwired keyboard controller and PS2 mouse interface, Real Time clock with 512B CMOS SRAM and two 8259A compatible Interrupt controllers. Besides, the I/O APIC managing up to 24 interrupts with both Serial and FSB interrupt delivery modes is supported.

The integrated PCI Express controllers feature two x1 ports. It complies with PCI Express 1.0a specification and supports 2.5Gb/s for each direction. The integrated power management module incorporates the ACPI 2.0 compliance functions, the APM 1.2 compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and power down events are also supported. 25 general purposed I/O pins are provided to give an easy to use logic for specific application. In addition, the SiS965L supports Deeper Sleep power state for Intel Mobile processor. For AMD processor, the SiS965L use the CPUSTP# signal to reduce processor voltage during C3 and S1 state.

A high bandwidth and mature SiS MuTIOL® 1G technology is incorporated to connect SiS MuTIOL® 1G North Bridge and SiS965L MuTIOL® 1G Media I/O together. SiS MuTIOL® 1G technology is developed into three layers, the Multi-threaded I/O Channels Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Channels layer, the Multi-threaded I/O Packet Layer in SiS965L to transfer data w/ 1GB/s bandwidth from/to Multi-threaded I/O Channels layer to/from SiS MuTIOL® 1G North Bridge, and the Multi-threaded I/O Packet Layer in SiS MuTIOL® 1G North Bridge to transfer data w/ 1GB/s from/to memory sub-system to/from the Multi-threaded I/O Packet Layer in SiS965L.